Folsom, California

Job Description

IP Engineering group builds leadership IP that power winning products for Intel. Analog and Mixed Signal Group Memory IP team within IP Engineering Group designs DDR PHY which is integrated on Client, Server and IOTG SOC product lines. This is an opportunity to work on cutting edge/leadership IP, interact with Architects/u-Architects/Designers and grow in to become a technical expert.

Responsibilities will include but not limited to:

  • Candidate will drive Electrical Validation methodology and perform the Electrical validation and System level silicon debug on DDR PHY Analog IPs
  • Candidate will be involved in pre-si verification of PHY using Mixed signal validation
  • Candidate will contribute to design of test feature definition
  • Candidate will coordinate and work with PHY circuit and logic team, Architects and uArchitects on silicon debug
  • Candidate will work on Pre-Silicon readiness such as Test scripts/flows, Test plan, Test Methodology, PHY Initialization and calibration sequences using Architecture and uArchitecture specs
  • Candidate will be responsible for debug and data quality and make sure the critical Electrical Validation data is collected and issues root caused in time for Product and Test chip Milestones
  • Candidate will also perform Pre-Silicon to Post-Silicon data comparison


  • Problem solving attitude
  • Ability to get work done by working with different people from various functions
  • Good communication skills and excellent team player


Candidate must possess below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualification:

Bachelors degree in Electrical Engineering, Computer Engineering, Computer Science or a closely related field and 3+ years of experience OR a Masters degree in Electrical Engineering, Computer Engineering, Computer Science or a closely related field and 2+ years of experience in Test development, and execution using lab equipment for analog mixed signal circuit characterization and debug

Preferred Qualifications:

  • Knowledge of Mixed Signal IP/DDR PHY
  • Experienced in use of Electrical validation equipment such as Bert, OscilloScope, Signal Generator, Keithley, Multimeter
  • Strong software scripting and programming skills in python
  • Familiarity with high frequency signal integrity concepts using frequency domain S-parameter and time domain metrics
  • Experience with Memory system level debug
Inside this Business Group

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Intel Corporation will require all new U.S. employees to be fully-vaccinated for Covid-19 as a condition of hire unless they have an approved accommodation in place under applicable law. Newly-hired employees will be required to provide proof of vaccination prior to their start date.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

See Job Description

Folsom, California

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