Austin, Texas

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Job Description:

This is a Technical Lead position for DSP/Systems Design Engineering for Serdes in the Physical Layer Products (PLP) Division. You will join a team of expert mixed-signal ASIC designers and help drive the design, verification, and implementation of advanced signal processing algorithms for the physical layer of high speed Serdes at speeds of 100G+. The types of algorithms that will be implemented include: PAM & other higher order modulation, single/multi-input adaptive equalizers/cancellers, single/multi-dimensioned FEC, digital filters, and interface/integration with analog functions and analysis and compensation for analog circuit non-linearities.

Responsibilities include:
  • Organizes, leads and facilitates cross-functional teams for development of High Speed DSP based Serdes
  • Analysis of customer requirements, definition of Serdes architecture, including analog and digital signal processing block requirements, simulation & verification models and post-Si lab test plan.
  • Develop and run system level simulation suites of the Serdes to evaluate architectural tradeoffs and predict performance
  • Bit-exact modeling of logic with MATLAB and C/C++ for simulation and verification with Digital RTL
  • Develop, test and debug firmware associated with physical layer functionality
  • Analysis of Results and debug of post-Si testing of Serdes
  • Documentation/application note development and customer support
  • Support marketing group with customer meetings and collateral

Job Requirements
  • M.S.E.E. with 13+ years experience is typical or comparable experience
  • Expert knowledge in Communication Theory
  • Expert knowledge in Digital Signal Processing algorithms and Adaptive control
  • Working knowledge of Analog circuit behavior
  • Working knowledge of Transmission line theory and s-parameters
  • Expert in MATLAB, C/C++ programming
  • Understanding test setup and equipment limitations and common hardware behavior is desired
  • Knowledge of IEEE 802.3 Ethernet Serdes specifications is desired
  • Experience in analysis and design of high-speed Clock and Data Recovery (CDR) is a plus.
  • Understanding of RTL implementation and constraints is a plus

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

Austin, Texas

Broadcom Inc. is a global infrastructure technology leader built on 50 years of innovation, collaboration and engineering excellence. With roots based in the rich technical heritage of AT&T/Bell Labs, Lucent and Hewlett-Packard/Agilent, Broadcom focuses on technologies that connect our world. Through the combination of industry leaders Broadcom, LSI, Broadcom Corporation, Brocade, CA Technologies and Symantec, the company has the size, scope and engineering talent to lead the industry into the future.

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