Summary

Posted: Oct 26, 2020

Role Number:200201402

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for an ambitious and exceptionally talented design verification engineer. As a member of our dynamic group, you will have the unique and rewarding opportunity to shape upcoming products that will delight and inspire millions of Apple’s customers every day. We are looking for a Design Verification Engineer who will enable bug-free first silicon for mixed-signal designs. The responsibilities include all phases of pre-silicon verification including, establishing design verification methodology, and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.

Key Qualifications

Key Qualifications

Deep knowledge of SystemVerilog test-bench language and UVM
Experience developing scalable and portable test-benches
Experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, coverage collection, gate level simulations
Experience with serial protocols such as PCIe or USB
Experience with mixed signal verification methodology for IPs such as PHYs, PLLs etc.
In lieu of UVM knowledge, C/C++ experienced level knowledge
Deep knowledge of one of the scripting languages: Python, Perl, TCL
Deep knowledge of formal verification methodology

Description

Description

In this role, you will be responsible for ensuring a bug-free first silicon for part of the SoC / IP and are expected to: Develop detailed test and coverage plans based on the micro-architecture. Develop verification methodology suitable for the IP, ensuring a scalable and portable environment. Develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage. Develop verification plans for all features under your care. Execute verification plans, including design bring-up, Design Verification environment bring-up, regression enabling for all features under your care, de-bug of the test failures. Develop block, IP and SoC level test-benches Track and report Design Verification progress using a variety of metrics, including bugs and coverage. Develop mixed-signal simulation environment, and work closely with analog team to ensure overall bug-free mixed-signal design.

Education & Experience

Education & Experience

Masters Degree+ 3 years of industrial experience Bachelors Degree+ 5 years of industrial experience

Additional Requirements

Additional Requirements

Design Verification Engineer - Military Veterans

Cupertino, CA

Cupertino, CA