Cupertino, California

Summary

Posted: Nov 20, 2020
Role Number:200039392
Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intellectual people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver groundbreaking Apple products. In this role, you will be at the center of a processor design effort collaborating with architecture, CAD, timing and logic design teams, with a critical exclusive processor designs.

Key Qualifications

Key Qualifications
  • You will have 10+ years of Physical Design experience on high performance CPU and/or SOC designs
  • Knowledge about industry standards and practices in Physical Design, including Physically aware synthesis and Place & Route Experience in developing and implementing Power grid and Clock specifications
  • Working Knowledge of Computer Architecture and HDL languages like verilog
  • Collaborate with logic design team for timing fixes Power user of industry standard Physical Design & Synthesis tools
  • Proven Understanding of scripting languages such as Perl/Tcl Working knowledge of Extraction and STA methodology tools
  • Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at block level

Description

Description
As a Lead Physical Design Methodology Engineer, you will be involved with all phases of physical design of high performance processor from RTL to delivery of our final GDSII. Your responsibilities include but are not limited to: • Generate Block/Chip level static timing constraints • Build block level floorplan including pin placement and power grid Perform block level place and route and close the design to meet timing, area and power constraints • Generate and Implement ECOs to fix timing, noise and EM IR violations • Run Physical design verification flow at block level and fix LVS/DRC violations • Participate in establishing CAD and physical design methodologies for correct by construction designs

Education & Experience

Education & Experience
BS/MS/PHD CE, EE, OR CS is required.

Additional Requirements

Additional Requirements

Cupertino, California

We’re a diverse collective of thinkers and doers, continually reimagining what’s possible to help us all do what we love in new ways. The people who work here have reinvented entire industries with the Mac, iPhone, iPad, and Apple Watch, as well as with services, including Apple TV, the App Store, Apple Music, and Apple Pay. And the same innovation that goes into our products also applies to our practices — strengthening our commitment to leave the world better than we found it.

Every new product we invent, service we create, or store we open is the result of people working together to make each other’s ideas stronger. That happens here because every one of us strives toward a common goal — creating the best customer experiences. So bring your passion, courage, and original thinking and get ready to share it. This is where your work can make a difference in people’s lives. Including your own.

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